FIG. 1 is an illustration of a conventional four transistor (4T) pixel 100. The pixel 100 includes a light sensitive element 101, shown as a photodiode, a floating diffusion node C, and four transistors: a transfer transistor 111, a reset transistor 112, a source follower transistor 113, and a row select transistor 114. The pixel 100 accepts a TX control signal for controlling the conductivity of the transfer transistor 111, a RST control signal for controlling the conductivity of the reset transistor 112, and a ROW control signal for controlling the conductivity of the row select transistor 114. The voltage at the floating diffusion node C controls the conductivity of the source follower transistor 113. The output of the source follow transistor 113 is presented at node B when the row select transistor 114 is conducting.
The states of the transfer and reset transistors 111, 112 determine whether the floating diffusion node C is coupled to the light sensitive element 101 for receiving a photo generated charge generated by the light sensitive element 101 following a charge integration period, or a source of pixel power VAAPIX from node A during a reset period.
The pixel 100 is operated as follows. The ROW control signal is asserted to cause the row select transistor 114 to conduct. At the same time, the RST control signal is asserted while the TX control signal is not asserted. This couples the floating diffusion node C to the pixel power VAAPIX at node A, and resets the voltage at node C to the pixel power VAAPIX. The pixel 100 outputs a reset signal Vrst at node B. As will be explained in greater detail below in connection with FIG. 2, node B is typically coupled to a column line 215 (FIG. 2) of an imager 200.
After the reset signal Vrst has been output, the RST control signal is not asserted. The light sensitive element 101 is exposed to incident light and accumulates charges based on the level of the incident light during a charge integration period. After the charge integration period, the TX control signal is asserted. This couples the floating diffusion node C to the light sensitive element 101. Charge flows through the transfer transistor 111 and diminishes the voltage at the floating diffusion node C. The pixel 100 outputs a photo signal Vsig at node B. The reset and photo signals Vrst, Vsig are different components of the overall pixel output (i.e., Voutput=Vrst−Vsig), which is typically processed by an imager 200 (FIG. 2) as explained in greater detail below.
FIG. 2 is an illustration of an imager 200 that includes a plurality of pixels 100, 100′ forming a pixel array 201. The pixel array 201 includes an outer region 201a of dark (i.e., non-image) pixels 100′ and an inner region 201b of image pixels 100. Due to space limitations the pixel array 201 is drawn as a 4×4 array. One skilled in the art would recognize that in most imagers 200, both the outer 201a and inner 201b regions of the pixel array 201 would ordinarily include many more pixels 100′, 100.
The dark pixels 100′ are essentially identical to the image pixels 100 (FIG. 1) except they are not used to capture an image. Typically, the light sensitive element 101 of a dark pixel 100′ is shielded from incident light. As shown in FIG. 2, dark pixels 100′ are also coupled to the column lines 215. In some imagers the outputs produced by the dark pixels 100′ are not further processed, while in other imagers the outputs are processed as non-image signals to provide a dark signal level.
The imager 200 also includes row circuitry 210, column circuitry 220, a digital conversion circuit 230, a digital processing circuit 240, and a storage device 250. The imager 200 also includes a controller 260. The row circuitry 210 selects a row of pixels 100, 100′ from the pixel array 201. The pixels 100, 100′ in the selected row output their reset and pixel signals Vrst, Vsig to the column circuitry 220, via column lines 215. The column circuit 220 samples and holds the reset and pixel signals Vrst, Vsig. For signals that were produced by an image pixel 100, the column circuitry 220 also forms the pixel output (Vrst−Vsig), which is presented to the digital conversion circuit 230 via lines 216. The digital conversion circuit 230 converts the pixel output signals to corresponding digital values, and may include for example, plural analog-to-digital converters. The digital values are then processed by the digital processing circuit 240, which stores the processed values in the storage device 250 (for output). The controller 260 is coupled to the pixel array 201, row circuitry 210, column circuitry 220, digital processing circuit 240, and storage device 250, and provides control signals to perform the above described processing. Signals which are produced from a non-image pixel 100′ are either not sampled and held and are not subsequently processed by the digital conversion circuit 230, digital processing circuit 240, nor stored in the storage device 250, or are sampled and held and processed to provide a dark signal level.)
A pixel 100 is susceptible to a type of distortion known as eclipsing. Eclipsing refers to the distortion arising when a pixel outputs a pixel signal corresponding to a dark pixel even though bright light is incident upon the pixel. Eclipsing can occur when a pixel is exposed to bright light, as the light sensitive element 101 can produce a large quantity of photogenerated charge. While the pixel 100 is outputting the reset signal Vrst, a portion of the photogenerated charge produced by the light sensitive element 101 during an ongoing integration period may spill over the transfer transistor 111 into the floating diffusion node C. This diminishes the reset voltage at the floating diffusion node and can causes the pixel 100 to output an incorrect (i.e., diminished voltage) reset signal Vrst. This, in turn, can cause the reset and photo signals Vrst, Vsig to be nearly the same voltage. For example, the photo and reset signals Vrst, Vsig may each be approximately 0 volts. The pixel output (Vrst−Vsig) can therefore become approximately 0 volts, which corresponds to an output voltage normally associated with a dark pixel. Eclipsing is not a concern with respect to the non-image pixels 100′ because their light sensitive elements 101 are shielded from incident light.
An anti-eclipse circuit can be used to minimize the effect of eclipsing. For example, since during an eclipse a pixel's reset voltage will tend to drop towards zero volts, an anti-eclipse circuit can monitor the voltage level of the reset signal. If the voltage level drop below a threshold voltage, the anti-eclipse circuit can assume the eclipsing may occur (or is occurring) and then correct the voltage level of the reset signal by pulling the reset level up to a correction voltage, thereby minimizing the eclipse effect.
FIG. 3 is a more detailed illustration of one implementation of the column circuitry 220 of FIG. 2 employing an anti eclipsing circuit. In the column circuitry 220, each column line 215 associated with an image pixel 100 is coupled, via node D, to an anti-eclipse (AE) circuit 310, a load circuit 390, and a sample and hold (SH) circuit 380. Each SH circuit 380 is also coupled, via line 216, to the digital conversion circuit 230 (FIG. 2). The load circuit 390 serves to stabilize the voltage at node D as the reset Vrst and photo Vsig signals travel between a pixel 100 and a load circuit 390 via the column line 215. The SH circuit 380 alternatively samples and holds the voltage at node D as the reset Vrst and photo Vsig signals are transmitted on column line 215 between the pixel 100 and the load circuit 390. The AE circuit 310 functions to minimize the effect of the eclipse distortion by monitoring the voltage at node D when the reset signal Vrst is conducted between the pixel 100 and the load circuit 390. If the voltage at node D drops below a predetermined threshold during the output of the reset signal Vrst, the AE circuit 310 intervenes by clamping the voltage of the reset signal Vrst to a predetermined voltage threshold. In this manner, eclipse distortion is minimized by ensuring that the reset voltage does not fall below the predetermined threshold. In the column circuitry 220, each column line 215 associated with an non-image pixel 100′ is just coupled to a corresponding load circuit 390. This implementation corresponds to an imager which does not further process non-image pixels 100′, although as previously noted, some imagers may process signals from non-image pixels 100′. As shown in FIG. 3, each AE circuit 310 accepts control signals AE_SHR and AE_Vref. The function of these signals will be explained below in connection with FIG. 4.
FIG. 4 is an illustration of an exemplary implementation of the AE circuit 310. The AE circuit 310 is used to selectively clamp node D to node E, thereby setting the voltage at node D to AE_Vref minus the threshold voltage of transistor 320 (transistor 330 is operating as a switch and should not appreciably affect the voltage level at node D). More specifically, if the pixel is outputting a reset signal and the reset signal level is below a predetermined voltage, the AE circuit 310 clamps the voltage at node D to AE_Vref minus the threshold voltages of transistor 320, thereby minimizing the effect of the eclipse distortion.
More specifically, the AE circuit 310 accepts pixel power VAAPIX at node E, which is coupled to one source/drain of an AE transistor 320. The AE transistor 320 is coupled in series a switch transistor 330, which in turn is coupled in series to node D. An AE threshold voltage AE_Vref is supplied to the gate of the AE transistor 320, while a control signal AE_SHR is supplied to the gate of the switch transistor 320.
The AE_SHR control signal is used to activate the AE circuit 310 by causing the AE transistor 330 to conduct only when the reset signal Vrst is being output by a pixel 100 and sampled by sample and hold circuit 380. The AE_SHR control signal may be, for example, identical to the SHR control signal generated by the control circuit 260 (FIG. 2) to control when the sample and hold circuit 380 (FIG. 3) samples and holds the reset signal Vrst. The AE_SHR control signal may be generated by the control circuit 260 (FIG. 2).
Now also referring to FIG. 5, it can be seen that the AE threshold voltage AE_Vref is generated by a circuit 500 from pixel power VAAPIX. The circuit 500 is typically a resistor based voltage divider which produces the AE threshold voltage AE_Vref from pixel power VAAPIX. In FIG. 5, the AE threshold voltage AE_Vref is controlled by the resistance of resistors 510 and 520. The AE threshold voltage AE_Vref is set to a predetermined level. If the voltage at node D drops below the level of the AE threshold voltage AE_Vref while the switch transistor 330 is conducting, the AE circuit 310 clamps the voltage at node D to AE_Vref minus the threshold voltage of transistor 320.
Thus, in order to provide an anti-eclipse function, the AE threshold voltage AE_Vref must be set at a proper level which corresponds to an offset from the nominal (i.e., not during an eclipse) reset signal voltage level of a pixel. Unfortunately, semiconductor fabrication produces variances in each integrated circuit. Differences associated with, for example, the amount of charge injected to the floating diffusion node C of a pixel during a reset operation, or threshold voltages of transistors, may alter nominal reset signal voltage level, and thus, the ideal voltage level for the AE threshold voltage AE_Vref. While such variances may be corrected by calibrating the voltage level of the AE threshold voltage signal, there is a desire and need for an anti-eclipse circuit which minimizes post manufacturing calibrations.